1. Technical Field
The present invention relates to a method of fabricating a semiconductor memory device, and more particularly, to a method of forming a lower electrode of a capacitor in a semiconductor memory device.
2. Discussion of Related Art
Generally, to increase a capacitor's capacitance, the surface area of the capacitor's electrodes must be increased, or high-k dielectrics may be used. A dielectric material often used includes SiO2 (permittivity: 3.9) and Si3N4 (permittivity: 7.0). A high-k dielectric material may include TiO2 (70˜80), Ta2O5 (24˜26), SrTiO3 (200˜300), and BST (300˜500). However, the high-k dielectric materials have many problems to be solved before being employed because they tend to cause a high leakage current.
As a method of increasing the surface area of a capacitor electrode, one may increase an effective area by forming recesses on the surface of the capacitor's electrode, and may also increase an effective area by structural characteristics. One method of forming recesses on the surface of a capacitor electrode is to form hemispherical grains on the surface of polysilicon by appropriately controlling deposition parameters. The structural method may be classified into a stack structure and a trench structure. The stack structure includes a fin structure, a cylinder structure, and a multilayer vertical stack structure.
A capacitor structure most commonly used as a high capacitance, highly-integrated memory structure is a cylinder structure having hemispherical grains. The cylinder structure is formed by a photolithography process after a sacrificial oxide layer is deposited. However, a portion of a lower structure for forming a capacitor lower electrode on a semiconductor substrate may be etched during processes of patterning and etching the sacrificial oxide layer, using a mask. That is, the sacrificial oxide layer interposed between a conductive layer deposited to form the lower electrode has a different etch rate from that of a mold oxide layer. Since an etch rate of the sacrificial oxide layer is higher, the conductive layer is exposed to an etch solution, and the etch solution is absorbed by the surface of the conductive layer and reaches a lower interlayer insulating layer. Thus, the etch solution etches the lower interlayer insulating layer, thereby causing an excessive etch phenomenon.
Hereinafter, a conventional method of forming a lower electrode of a capacitor involved with the excessive etch phenomenon will be explained in reference to attached drawings.
FIGS. 1A to 1C are cross-sectional views sequentially illustrating a mechanism of the excessive etch phenomenon in a conventional method of forming a capacitor lower electrode. FIG. 1A is a cross-sectional view illustrating that an etch hole is formed after a mold oxide is etched, and a first conductive layer is deposited on the surface of the etch hole. FIG. 1B is a cross-sectional view illustrating that a second conductive layer is deposited on the surface of the first conductive layer of FIG. 1A, and a sacrificial oxide layer is interposed between the two conductive layers. FIG. 1C is a cross-sectional view illustrating that an excessive etch phenomenon occurs due to difference of etch rates of the sacrificial oxide layer and the mold oxide of FIG. 1B.
FIG. 1D is a photograph illustrating that a hole is formed in an interlayer insulating layer due to the excessive etch phenomenon shown in FIG. 1C. FIG. 1E is a cross-sectional view illustrating that capacitor lower electrodes are inclined due to the excessive etch phenomenon shown in FIG. 1C. FIG. 1F is a photograph illustrating that a leaning hole phenomenon (a so-called eyebrow defect phenomenon) occurs due to the leaning phenomenon of FIG. 1E.
In view of the excessive etch phenomenon in reference to FIGS. 1A to 1F, a lower structure for forming the capacitor lower electrode is formed on the semiconductor substrate. That is, a buried contact 8 composed of polysilicon is formed to be connected with a transistor of a memory cell on the semiconductor substrate. An etch stop layer 4 is formed on the buried contact 8 to restrict an etch range, and a mold oxide layer 2 is formed on the etch stop layer 4. Here, the etch stop layer 4 is normally composed of silicon nitride (SiN). The mold oxide layer 2 is normally composed of a BPSG insulating layer and a TEOS insulating layer.
Then, a series of photolithography processes is performed on the mold oxide layer 2, thereby forming an etch hole. Next, a first conductive layer 10 is deposited on the overall surface of the etch hole. The first conductive layer 10 and the buried contact 8 react during deposition of the first conductive layer 10, thereby forming a TiSix (for example, TiSi2) layer 7.
A second conductive layer 12 as a prototype of a cylinder-structured lower electrode is deposited on the surface of the first conductive layer 10. A sacrificial oxide layer 14 is interposed between the walls of the second conductive layer 12. The sacrificial oxide layer 14 prevents the second conductive layer 12 from being exposed to an etch solution, and prevents an interlayer insulating layer 6 and the TiSix layer 7 from being etched, and is ultimately removed by an LAL solution.
When the sacrificial oxide layer 14 is etched using an etch solution (in this case, a method of removal using an LAL solution is normally used.), the sacrificial oxide layer 14 and the mold oxide layer 2 have different etch rates. That is, the sacrificial oxide layer 14 is etched faster than the mold oxide layer 2. Thus, while the second conductive layer 12 of the cylinder-structured capacitor lower electrode is exposed and the mold oxide layer 2 is etched, the etch solution penetrates through into the second conductive layer 12 and the first conductive layer 10 and reaches the TiSix layer 7 and the interlayer insulating layer 6, thereby sequentially etching the TiSix layer 7 and the interlayer insulating layer 6.
As described above, since the sacrificial oxide layer 14 is first etched before the mold oxide layer 2 in the conventional method of forming a lower electrode of a capacitor, a problem occurs of an excessive etch phenomenon where the interlayer insulating layer and the TiSix layer of the cylinder-structured capacitor lower electrode are etched (see, e.g., FIG. 1C at 16).
Further, a leaning hole phenomenon occurs due to the excessive etch phenomenon, in which the cylinder-structured capacitor lower electrodes are inclined, thereby causing failures of the capacitor lower electrodes (see, e.g., FIG. 1B at 12a), interfering with production yields of these semiconductor memory devices.